TriEye

RTL Design Engineer

Join our core team in Tel-Aviv and build the future together with us.

In this role, you will be responsible for:
-Writing detailed design specification and test plans for brand new modules designed from scratch
-Working in close collaboration with algorithms developers, architects, analog designers and verification engineers.
-Providing high-quality RTL description for the design.
-Supporting design verification to insure bug-free first silicon.
-Driving functional and code coverage as well as timing closure for your designs.
-Supporting silicon bring-up, performance and power characterization

Required Qualifications:
Two or more years of experience in logic design with the following qualifications:
-RTL design using Verilog or SystemVerilog
-Design of state machines, data paths, arbitration and clock domain crossing logic
-Understanding of logic synthesis, timing constraints
-Exposure to Design for Test, understanding of scan concept and writing DFT friendly RTL
-Experience with bus protocols like AHB, APB
-Previous experience in design of image sensor SoC is advantage
-BSc, or MSc degree in Electrical Engineering, Computer Engineering, or Computer Science

Send CV’s to careers@trieye.tech with the position in the title.